MPU6050.h file
MPU6050 I2C device class.
Classes
- class MPU6050
Defines
- #define pgm_read_byte(addr)
- #define MPU6050_INCLUDE_DMP_MOTIONAPPS20
- #define MPU6050_ADDRESS_AD0_LOW
- #define MPU6050_ADDRESS_AD0_HIGH
- #define MPU6050_DEFAULT_ADDRESS
- #define MPU6050_RA_XG_OFFS_TC
- #define MPU6050_RA_YG_OFFS_TC
- #define MPU6050_RA_ZG_OFFS_TC
- #define MPU6050_RA_X_FINE_GAIN
- #define MPU6050_RA_Y_FINE_GAIN
- #define MPU6050_RA_Z_FINE_GAIN
- #define MPU6050_RA_XA_OFFS_H
- #define MPU6050_RA_XA_OFFS_L_TC
- #define MPU6050_RA_YA_OFFS_H
- #define MPU6050_RA_YA_OFFS_L_TC
- #define MPU6050_RA_ZA_OFFS_H
- #define MPU6050_RA_ZA_OFFS_L_TC
- #define MPU6050_RA_SELF_TEST_X
- #define MPU6050_RA_SELF_TEST_Y
- #define MPU6050_RA_SELF_TEST_Z
- #define MPU6050_RA_SELF_TEST_A
- #define MPU6050_RA_XG_OFFS_USRH
- #define MPU6050_RA_XG_OFFS_USRL
- #define MPU6050_RA_YG_OFFS_USRH
- #define MPU6050_RA_YG_OFFS_USRL
- #define MPU6050_RA_ZG_OFFS_USRH
- #define MPU6050_RA_ZG_OFFS_USRL
- #define MPU6050_RA_SMPLRT_DIV
- #define MPU6050_RA_CONFIG
- #define MPU6050_RA_GYRO_CONFIG
- #define MPU6050_RA_ACCEL_CONFIG
- #define MPU6050_RA_FF_THR
- #define MPU6050_RA_FF_DUR
- #define MPU6050_RA_MOT_THR
- #define MPU6050_RA_MOT_DUR
- #define MPU6050_RA_ZRMOT_THR
- #define MPU6050_RA_ZRMOT_DUR
- #define MPU6050_RA_FIFO_EN
- #define MPU6050_RA_I2C_MST_CTRL
- #define MPU6050_RA_I2C_SLV0_ADDR
- #define MPU6050_RA_I2C_SLV0_REG
- #define MPU6050_RA_I2C_SLV0_CTRL
- #define MPU6050_RA_I2C_SLV1_ADDR
- #define MPU6050_RA_I2C_SLV1_REG
- #define MPU6050_RA_I2C_SLV1_CTRL
- #define MPU6050_RA_I2C_SLV2_ADDR
- #define MPU6050_RA_I2C_SLV2_REG
- #define MPU6050_RA_I2C_SLV2_CTRL
- #define MPU6050_RA_I2C_SLV3_ADDR
- #define MPU6050_RA_I2C_SLV3_REG
- #define MPU6050_RA_I2C_SLV3_CTRL
- #define MPU6050_RA_I2C_SLV4_ADDR
- #define MPU6050_RA_I2C_SLV4_REG
- #define MPU6050_RA_I2C_SLV4_DO
- #define MPU6050_RA_I2C_SLV4_CTRL
- #define MPU6050_RA_I2C_SLV4_DI
- #define MPU6050_RA_I2C_MST_STATUS
- #define MPU6050_RA_INT_PIN_CFG
- #define MPU6050_RA_INT_ENABLE
- #define MPU6050_RA_DMP_INT_STATUS
- #define MPU6050_RA_INT_STATUS
- #define MPU6050_RA_ACCEL_XOUT_H
- #define MPU6050_RA_ACCEL_XOUT_L
- #define MPU6050_RA_ACCEL_YOUT_H
- #define MPU6050_RA_ACCEL_YOUT_L
- #define MPU6050_RA_ACCEL_ZOUT_H
- #define MPU6050_RA_ACCEL_ZOUT_L
- #define MPU6050_RA_TEMP_OUT_H
- #define MPU6050_RA_TEMP_OUT_L
- #define MPU6050_RA_GYRO_XOUT_H
- #define MPU6050_RA_GYRO_XOUT_L
- #define MPU6050_RA_GYRO_YOUT_H
- #define MPU6050_RA_GYRO_YOUT_L
- #define MPU6050_RA_GYRO_ZOUT_H
- #define MPU6050_RA_GYRO_ZOUT_L
- #define MPU6050_RA_EXT_SENS_DATA_00
- #define MPU6050_RA_EXT_SENS_DATA_01
- #define MPU6050_RA_EXT_SENS_DATA_02
- #define MPU6050_RA_EXT_SENS_DATA_03
- #define MPU6050_RA_EXT_SENS_DATA_04
- #define MPU6050_RA_EXT_SENS_DATA_05
- #define MPU6050_RA_EXT_SENS_DATA_06
- #define MPU6050_RA_EXT_SENS_DATA_07
- #define MPU6050_RA_EXT_SENS_DATA_08
- #define MPU6050_RA_EXT_SENS_DATA_09
- #define MPU6050_RA_EXT_SENS_DATA_10
- #define MPU6050_RA_EXT_SENS_DATA_11
- #define MPU6050_RA_EXT_SENS_DATA_12
- #define MPU6050_RA_EXT_SENS_DATA_13
- #define MPU6050_RA_EXT_SENS_DATA_14
- #define MPU6050_RA_EXT_SENS_DATA_15
- #define MPU6050_RA_EXT_SENS_DATA_16
- #define MPU6050_RA_EXT_SENS_DATA_17
- #define MPU6050_RA_EXT_SENS_DATA_18
- #define MPU6050_RA_EXT_SENS_DATA_19
- #define MPU6050_RA_EXT_SENS_DATA_20
- #define MPU6050_RA_EXT_SENS_DATA_21
- #define MPU6050_RA_EXT_SENS_DATA_22
- #define MPU6050_RA_EXT_SENS_DATA_23
- #define MPU6050_RA_MOT_DETECT_STATUS
- #define MPU6050_RA_I2C_SLV0_DO
- #define MPU6050_RA_I2C_SLV1_DO
- #define MPU6050_RA_I2C_SLV2_DO
- #define MPU6050_RA_I2C_SLV3_DO
- #define MPU6050_RA_I2C_MST_DELAY_CTRL
- #define MPU6050_RA_SIGNAL_PATH_RESET
- #define MPU6050_RA_MOT_DETECT_CTRL
- #define MPU6050_RA_USER_CTRL
- #define MPU6050_RA_PWR_MGMT_1
- #define MPU6050_RA_PWR_MGMT_2
- #define MPU6050_RA_BANK_SEL
- #define MPU6050_RA_MEM_START_ADDR
- #define MPU6050_RA_MEM_R_W
- #define MPU6050_RA_DMP_CFG_1
- #define MPU6050_RA_DMP_CFG_2
- #define MPU6050_RA_FIFO_COUNTH
- #define MPU6050_RA_FIFO_COUNTL
- #define MPU6050_RA_FIFO_R_W
- #define MPU6050_RA_WHO_AM_I
- #define MPU6050_SELF_TEST_XA_1_BIT
- #define MPU6050_SELF_TEST_XA_1_LENGTH
- #define MPU6050_SELF_TEST_XA_2_BIT
- #define MPU6050_SELF_TEST_XA_2_LENGTH
- #define MPU6050_SELF_TEST_YA_1_BIT
- #define MPU6050_SELF_TEST_YA_1_LENGTH
- #define MPU6050_SELF_TEST_YA_2_BIT
- #define MPU6050_SELF_TEST_YA_2_LENGTH
- #define MPU6050_SELF_TEST_ZA_1_BIT
- #define MPU6050_SELF_TEST_ZA_1_LENGTH
- #define MPU6050_SELF_TEST_ZA_2_BIT
- #define MPU6050_SELF_TEST_ZA_2_LENGTH
- #define MPU6050_SELF_TEST_XG_1_BIT
- #define MPU6050_SELF_TEST_XG_1_LENGTH
- #define MPU6050_SELF_TEST_YG_1_BIT
- #define MPU6050_SELF_TEST_YG_1_LENGTH
- #define MPU6050_SELF_TEST_ZG_1_BIT
- #define MPU6050_SELF_TEST_ZG_1_LENGTH
- #define MPU6050_TC_PWR_MODE_BIT
- #define MPU6050_TC_OFFSET_BIT
- #define MPU6050_TC_OFFSET_LENGTH
- #define MPU6050_TC_OTP_BNK_VLD_BIT
- #define MPU6050_VDDIO_LEVEL_VLOGIC
- #define MPU6050_VDDIO_LEVEL_VDD
- #define MPU6050_CFG_EXT_SYNC_SET_BIT
- #define MPU6050_CFG_EXT_SYNC_SET_LENGTH
- #define MPU6050_CFG_DLPF_CFG_BIT
- #define MPU6050_CFG_DLPF_CFG_LENGTH
- #define MPU6050_EXT_SYNC_DISABLED
- #define MPU6050_EXT_SYNC_TEMP_OUT_L
- #define MPU6050_EXT_SYNC_GYRO_XOUT_L
- #define MPU6050_EXT_SYNC_GYRO_YOUT_L
- #define MPU6050_EXT_SYNC_GYRO_ZOUT_L
- #define MPU6050_EXT_SYNC_ACCEL_XOUT_L
- #define MPU6050_EXT_SYNC_ACCEL_YOUT_L
- #define MPU6050_EXT_SYNC_ACCEL_ZOUT_L
- #define MPU6050_DLPF_BW_256
- #define MPU6050_DLPF_BW_188
- #define MPU6050_DLPF_BW_98
- #define MPU6050_DLPF_BW_42
- #define MPU6050_DLPF_BW_20
- #define MPU6050_DLPF_BW_10
- #define MPU6050_DLPF_BW_5
- #define MPU6050_GCONFIG_FS_SEL_BIT
- #define MPU6050_GCONFIG_FS_SEL_LENGTH
- #define MPU6050_GYRO_FS_250
- #define MPU6050_GYRO_FS_500
- #define MPU6050_GYRO_FS_1000
- #define MPU6050_GYRO_FS_2000
- #define MPU6050_ACONFIG_XA_ST_BIT
- #define MPU6050_ACONFIG_YA_ST_BIT
- #define MPU6050_ACONFIG_ZA_ST_BIT
- #define MPU6050_ACONFIG_AFS_SEL_BIT
- #define MPU6050_ACONFIG_AFS_SEL_LENGTH
- #define MPU6050_ACONFIG_ACCEL_HPF_BIT
- #define MPU6050_ACONFIG_ACCEL_HPF_LENGTH
- #define MPU6050_ACCEL_FS_2
- #define MPU6050_ACCEL_FS_4
- #define MPU6050_ACCEL_FS_8
- #define MPU6050_ACCEL_FS_16
- #define MPU6050_DHPF_RESET
- #define MPU6050_DHPF_5
- #define MPU6050_DHPF_2P5
- #define MPU6050_DHPF_1P25
- #define MPU6050_DHPF_0P63
- #define MPU6050_DHPF_HOLD
- #define MPU6050_TEMP_FIFO_EN_BIT
- #define MPU6050_XG_FIFO_EN_BIT
- #define MPU6050_YG_FIFO_EN_BIT
- #define MPU6050_ZG_FIFO_EN_BIT
- #define MPU6050_ACCEL_FIFO_EN_BIT
- #define MPU6050_SLV2_FIFO_EN_BIT
- #define MPU6050_SLV1_FIFO_EN_BIT
- #define MPU6050_SLV0_FIFO_EN_BIT
- #define MPU6050_MULT_MST_EN_BIT
- #define MPU6050_WAIT_FOR_ES_BIT
- #define MPU6050_SLV_3_FIFO_EN_BIT
- #define MPU6050_I2C_MST_P_NSR_BIT
- #define MPU6050_I2C_MST_CLK_BIT
- #define MPU6050_I2C_MST_CLK_LENGTH
- #define MPU6050_CLOCK_DIV_348
- #define MPU6050_CLOCK_DIV_333
- #define MPU6050_CLOCK_DIV_320
- #define MPU6050_CLOCK_DIV_308
- #define MPU6050_CLOCK_DIV_296
- #define MPU6050_CLOCK_DIV_286
- #define MPU6050_CLOCK_DIV_276
- #define MPU6050_CLOCK_DIV_267
- #define MPU6050_CLOCK_DIV_258
- #define MPU6050_CLOCK_DIV_500
- #define MPU6050_CLOCK_DIV_471
- #define MPU6050_CLOCK_DIV_444
- #define MPU6050_CLOCK_DIV_421
- #define MPU6050_CLOCK_DIV_400
- #define MPU6050_CLOCK_DIV_381
- #define MPU6050_CLOCK_DIV_364
- #define MPU6050_I2C_SLV_RW_BIT
- #define MPU6050_I2C_SLV_ADDR_BIT
- #define MPU6050_I2C_SLV_ADDR_LENGTH
- #define MPU6050_I2C_SLV_EN_BIT
- #define MPU6050_I2C_SLV_BYTE_SW_BIT
- #define MPU6050_I2C_SLV_REG_DIS_BIT
- #define MPU6050_I2C_SLV_GRP_BIT
- #define MPU6050_I2C_SLV_LEN_BIT
- #define MPU6050_I2C_SLV_LEN_LENGTH
- #define MPU6050_I2C_SLV4_RW_BIT
- #define MPU6050_I2C_SLV4_ADDR_BIT
- #define MPU6050_I2C_SLV4_ADDR_LENGTH
- #define MPU6050_I2C_SLV4_EN_BIT
- #define MPU6050_I2C_SLV4_INT_EN_BIT
- #define MPU6050_I2C_SLV4_REG_DIS_BIT
- #define MPU6050_I2C_SLV4_MST_DLY_BIT
- #define MPU6050_I2C_SLV4_MST_DLY_LENGTH
- #define MPU6050_MST_PASS_THROUGH_BIT
- #define MPU6050_MST_I2C_SLV4_DONE_BIT
- #define MPU6050_MST_I2C_LOST_ARB_BIT
- #define MPU6050_MST_I2C_SLV4_NACK_BIT
- #define MPU6050_MST_I2C_SLV3_NACK_BIT
- #define MPU6050_MST_I2C_SLV2_NACK_BIT
- #define MPU6050_MST_I2C_SLV1_NACK_BIT
- #define MPU6050_MST_I2C_SLV0_NACK_BIT
- #define MPU6050_INTCFG_INT_LEVEL_BIT
- #define MPU6050_INTCFG_INT_OPEN_BIT
- #define MPU6050_INTCFG_LATCH_INT_EN_BIT
- #define MPU6050_INTCFG_INT_RD_CLEAR_BIT
- #define MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT
- #define MPU6050_INTCFG_FSYNC_INT_EN_BIT
- #define MPU6050_INTCFG_I2C_BYPASS_EN_BIT
- #define MPU6050_INTCFG_CLKOUT_EN_BIT
- #define MPU6050_INTMODE_ACTIVEHIGH
- #define MPU6050_INTMODE_ACTIVELOW
- #define MPU6050_INTDRV_PUSHPULL
- #define MPU6050_INTDRV_OPENDRAIN
- #define MPU6050_INTLATCH_50USPULSE
- #define MPU6050_INTLATCH_WAITCLEAR
- #define MPU6050_INTCLEAR_STATUSREAD
- #define MPU6050_INTCLEAR_ANYREAD
- #define MPU6050_INTERRUPT_FF_BIT
- #define MPU6050_INTERRUPT_MOT_BIT
- #define MPU6050_INTERRUPT_ZMOT_BIT
- #define MPU6050_INTERRUPT_FIFO_OFLOW_BIT
- #define MPU6050_INTERRUPT_I2C_MST_INT_BIT
- #define MPU6050_INTERRUPT_PLL_RDY_INT_BIT
- #define MPU6050_INTERRUPT_DMP_INT_BIT
- #define MPU6050_INTERRUPT_DATA_RDY_BIT
- #define MPU6050_DMPINT_5_BIT
- #define MPU6050_DMPINT_4_BIT
- #define MPU6050_DMPINT_3_BIT
- #define MPU6050_DMPINT_2_BIT
- #define MPU6050_DMPINT_1_BIT
- #define MPU6050_DMPINT_0_BIT
- #define MPU6050_MOTION_MOT_XNEG_BIT
- #define MPU6050_MOTION_MOT_XPOS_BIT
- #define MPU6050_MOTION_MOT_YNEG_BIT
- #define MPU6050_MOTION_MOT_YPOS_BIT
- #define MPU6050_MOTION_MOT_ZNEG_BIT
- #define MPU6050_MOTION_MOT_ZPOS_BIT
- #define MPU6050_MOTION_MOT_ZRMOT_BIT
- #define MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT
- #define MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT
- #define MPU6050_DELAYCTRL_I2C_SLV3_DLY_EN_BIT
- #define MPU6050_DELAYCTRL_I2C_SLV2_DLY_EN_BIT
- #define MPU6050_DELAYCTRL_I2C_SLV1_DLY_EN_BIT
- #define MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT
- #define MPU6050_PATHRESET_GYRO_RESET_BIT
- #define MPU6050_PATHRESET_ACCEL_RESET_BIT
- #define MPU6050_PATHRESET_TEMP_RESET_BIT
- #define MPU6050_DETECT_ACCEL_ON_DELAY_BIT
- #define MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH
- #define MPU6050_DETECT_FF_COUNT_BIT
- #define MPU6050_DETECT_FF_COUNT_LENGTH
- #define MPU6050_DETECT_MOT_COUNT_BIT
- #define MPU6050_DETECT_MOT_COUNT_LENGTH
- #define MPU6050_DETECT_DECREMENT_RESET
- #define MPU6050_DETECT_DECREMENT_1
- #define MPU6050_DETECT_DECREMENT_2
- #define MPU6050_DETECT_DECREMENT_4
- #define MPU6050_USERCTRL_DMP_EN_BIT
- #define MPU6050_USERCTRL_FIFO_EN_BIT
- #define MPU6050_USERCTRL_I2C_MST_EN_BIT
- #define MPU6050_USERCTRL_I2C_IF_DIS_BIT
- #define MPU6050_USERCTRL_DMP_RESET_BIT
- #define MPU6050_USERCTRL_FIFO_RESET_BIT
- #define MPU6050_USERCTRL_I2C_MST_RESET_BIT
- #define MPU6050_USERCTRL_SIG_COND_RESET_BIT
- #define MPU6050_PWR1_DEVICE_RESET_BIT
- #define MPU6050_PWR1_SLEEP_BIT
- #define MPU6050_PWR1_CYCLE_BIT
- #define MPU6050_PWR1_TEMP_DIS_BIT
- #define MPU6050_PWR1_CLKSEL_BIT
- #define MPU6050_PWR1_CLKSEL_LENGTH
- #define MPU6050_CLOCK_INTERNAL
- #define MPU6050_CLOCK_PLL_XGYRO
- #define MPU6050_CLOCK_PLL_YGYRO
- #define MPU6050_CLOCK_PLL_ZGYRO
- #define MPU6050_CLOCK_PLL_EXT32K
- #define MPU6050_CLOCK_PLL_EXT19M
- #define MPU6050_CLOCK_KEEP_RESET
- #define MPU6050_PWR2_LP_WAKE_CTRL_BIT
- #define MPU6050_PWR2_LP_WAKE_CTRL_LENGTH
- #define MPU6050_PWR2_STBY_XA_BIT
- #define MPU6050_PWR2_STBY_YA_BIT
- #define MPU6050_PWR2_STBY_ZA_BIT
- #define MPU6050_PWR2_STBY_XG_BIT
- #define MPU6050_PWR2_STBY_YG_BIT
- #define MPU6050_PWR2_STBY_ZG_BIT
- #define MPU6050_WAKE_FREQ_1P25
- #define MPU6050_WAKE_FREQ_2P5
- #define MPU6050_WAKE_FREQ_5
- #define MPU6050_WAKE_FREQ_10
- #define MPU6050_BANKSEL_PRFTCH_EN_BIT
- #define MPU6050_BANKSEL_CFG_USER_BANK_BIT
- #define MPU6050_BANKSEL_MEM_SEL_BIT
- #define MPU6050_BANKSEL_MEM_SEL_LENGTH
- #define MPU6050_WHO_AM_I_BIT
- #define MPU6050_WHO_AM_I_LENGTH
- #define MPU6050_DMP_MEMORY_BANKS
- #define MPU6050_DMP_MEMORY_BANK_SIZE
- #define MPU6050_DMP_MEMORY_CHUNK_SIZE